Compound semiconductor device and method for manufacturing the same

ABSTRACT

The invention provides a method for manufacturing a gallium nitride-based III-V group compound semiconductor device, which comprises the following steps: forming a semiconductor stacked structure over a substrate, wherein the semiconductor stacked structure comprises an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; etching the semiconductor stacked structure to expose a part of the n-type semiconductor layer; forming a first electrode on the n-type semiconductor layer, wherein the first electrode comprises an ohmic contact layer, a barrier layer, and a pad layer; performing an annealing process to lower the contact resistance between the first electrode and the n-type semiconductor layer and activate the p-type semiconductor layer at the same time; and forming a second electrode on the p-type semiconductor layer.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This is a divisional application of co-pending prior U.S.application Ser. No. 09/671,946, filed on Sep. 27, 2000. Thisapplication is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to a gallium nitride-based III-V groupcompound semiconductor device and method for manufacturing the same.

[0004] 2. Description of the Related Art

[0005] Since epitaxial layers of III-V group nitride such as galliumnitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride(InGaN), and aluminum indium gallium nitride (AlInGaN) were first grownsuccessfully, they have become promising materials for use in hightemperature/high power electronic devices and opotoelectronic devices,due to their high direct band gap, high saturation drift velocity, highbreakdown field, and chemical inertness. Recent improvements in crystalquality of epitaxial layers with increased dopant concentrations haveled to high quality laser diodes, light-emitting diodes, photodetectors,and microwave field effect transistors having been developed based onthese epitaxial III-V group nitride structures.

[0006] In general, the performance of III-V group nitride device hasbeen limited by contact resistance. Therefore, a key technology inachieving higher performance for III-V group nitride devices is therealization of more reliable metal contacts. Although a wide groupnitride devices is the realization of more reliable metal contacts.Although a wide variety of metals used as contacts with GaN have beenreported, the metallic titanium/aluminum (Ti/Al) bilayer has been mostwidely used as a conventional ohmic contact for n-type GaN. However,such a Ti/Al bilayer is prone to oxidation, which in turn leads to highohmic resistance during the fabrication process and during operation.

[0007] To avoid the oxidation propensity at elevated temperatures, a lowresistivity gold (Au) layer should be effective for passivating theTi/Al bilayer. However, gold would interdiffuse and penetrate into theGaN semiconductor layer, causing deterioration in thermal stability, andohmic contact property of the semiconductor device.

[0008]FIG. 1 is a cross-sectional view showing a typical structure of aGaN-based III-V group compound semiconductor light-emitting device (LED)100.

[0009] As shown in FIG. 1, an LED 100 includes an insulated substrate 1made of such as sapphire. The substrate 1 has a first major surface 1 aand a second major surface 1 b. A GaN buffer layer 2 is formed on thefirst major surface 1 a of the substrate 1. An n-type GaN-based III-Vgroup compound semiconductor layer 3 is formed on the buffer layer 2.The n-type semiconductor layer 3 is doped by n-type dopants such asgermanium (Ge), selenium (Se), sulfur (S), or tellurium (Te). Inaddition, the n-type semiconductor layer 3 can be doped by silicon (Si).

[0010] An n-type AlGaN layer 4 is formed on the n-type semiconductorlayer 3. An active layer 5 is formed on the n-type AlGaN layer 4, andthe active layer 5 has a multiple quantum well (MQW) structure, a singlequantum well (SQW) structure, or a double-heterostructure (DH) made ofsuch as InGaN/GaN. A p-type AlGaN layer 6 is formed on the active layer5. The p-type AlGaN layer 6 is doped with p-type dopants such asberyllium (Be), strontium (Sr), barium (Ba), zinc (Zn), or magnesium.

[0011] A p-type GaN-based III-V group compound semiconductor layer 7 isformed on the p-type AlGaN layer 6. The p-type semiconductor layer 7 isdoped with p-type dopants such as beryllium, strontium, barium, zinc, ormagnesium.

[0012] As shown in FIG. 1, the LED 100 includes an electrode 8A formedon the n-type semiconductor layer 3 and an electrode 8B formed on thep-type semiconductor layer 7. Conventionally, the electrode 8A includesa metal such as titanium, aluminum, or gold as mentioned above. Theelectrode 8B is a kind of ohmic electrode, it includes a metal such asnickel (Ni), chromium (Cr), gold or platinum.

[0013] Referring to FIG. 2, the flow chart shows conventional steps formanufacturing a light-emitting device 100.

[0014] First, as shown in step 201, a buffer layer 2, an n-typesemiconductor layer 3, an n-type AlGaN layer 4, an active layer 5, ap-type AlGaN layer 6, and a p-type semiconductor layer 7 are formed on asubstrate 1 in this order.

[0015] Next, as shown in step 202, a thermal process is performed toactivate the p-type AlGaN layer 6 and the p-type semiconductor layer 7.Since doped magnesium atoms in the p-type AlGaN layer 6 and p-typesemiconductor layer 7 form Mg—H bonds, holes are not provided. Thethermal process is to break the Mg—H bonds and activate the p-type AlGaNlayer 6 and p-type semiconductor layer 7. The thermal process isperformed at a temperature ranging from 650 to 780° C. for 15 to 60minutes.

[0016] Then, as shown in step 203, the p-type semiconductor layer 7,p-type AlGaN layer 6, active layer 5, and n-type AlGaN layer 4 arepartially etched away to expose a surface of the n-type semiconductorlayer 3. Here, a part of the n-type semiconductor layer 3 is also etchedaway.

[0017] Next, as shown in step 204, electrodes 8A and SB are formed,wherein the electrode 8A is formed on the n-type semiconductor layer 3,and the electrode 8B is formed on the p-type semiconductor layer 7. Theelectrodes 8A and 8B can be formed by known deposition methods such asevaporation or sputtering.

[0018] Next, as shown in step 205, an annealing process is performed.The object of this step is to lower the ohmic contact resistance of theelectrodes 8A and 8B. The annealing process is generally performed at atemperature ranging from 300 to 600° C.

[0019] It should be noted that besides forming the electrodes 8A and 8Bat the same time as mentioned in step 204, it can also be first formingthe electrode 8A, and after the annealing process, forming the electrode8B.

SUMMARY OF THE INVENTION

[0020] The invention provides a method for manufacturing a galliumnitride-based III-V group compound semiconductor device, includes thefollowing steps: providing a substrate having a first and a second majorsurfaces; forming a semiconductor stacked structure over the first majorsurface of the substrate, wherein the semiconductor stacked structureincludes an n-type gallium nitride-based III-V group compoundsemiconductor layer, an active layer, and a p-type gallium nitride-basedIII-V group compound semiconductor layer; etching the semiconductorstacked structure to expose a part of the n-type semiconductor layer;forming a first electrode on the n-type semiconductor layer, wherein thefirst electrode includes an ohmic contact layer, a barrier layer overthe ohmic contact layer, and a pad layer over the barrier layer; andperforming an annealing process for lowering the contact resistancebetween the first electrode and the n-type semiconductor layer, andactivating the p-type semiconductor layer simultaneously; and forming asecond electrode on the p-type semiconductor layer.

[0021] A gallium nitride-based III-V group compound semiconductor devicein accordance with an embodiment of the invention includes an n-typegallium nitride-based III-V group compound semiconductor layer; and anelectrode on the n-type gallium nitride-based III-V group compoundsemiconductor layer, and the electrode includes an ohmic contact layer,a barrier layer over the ohmic contact layer, and a pad layer over thebarrier layer.

[0022] A gallium nitride-based III-V group compound semiconductor devicein accordance with another embodiment of the invention includes asubstrate having a first and a second major surfaces; a semiconductorstacked structure formed over the first major surface of the substrateand which includes an n-type gallium nitride-based III-V group compoundsemiconductor layer, an active layer, and a p-type gallium nitride-basedIII-V group compound semiconductor layer; a first electrode on then-type semiconductor layer and which includes an ohmic contact layer, abarrier layer over the ohmic contact layer, and a pad layer over thebarrier layer; and a second electrode on the p-type semiconductor layer.

[0023] The ohmic contact of the n-type GaN of the invention has thermalstability endurance much better than that of a conventional Ti/Al/Aumultilayer. Therefore, the method for manufacturing the compoundsemiconductor device of the invention is simpler than the conventionalmethod, and can thus lower the costs and increase the yield.

BRIEF DESCRIPTION OF DRAWINGS

[0024]FIG. 1 is a cross-sectional view showing a GaN-based III-V groupcompound semiconductor light-emitting device in accordance with theinvention;

[0025]FIG. 2 is a flow chart showing fabrication steps for aconventional light-emitting device 100;

[0026]FIG. 3 is a cross-sectional view showing the structure ofelectrode of the invention;

[0027]FIG. 4 is a graph showing the dependence of specific contactresistance on annealing time at various annealing temperatures for theelectrode Ti/AIPt/Au in contact with n-type GaN;

[0028]FIG. 5 is a graph showing the dependence of specific contactresistance on annealing time at various annealing temperatures for theelectrode Ti/Al/Pt/Au in contact with unrecovered Si-implanted n-typeGaN;

[0029]FIG. 6 is a graph showing the dependence of specific contactresistance on annealing time at various annealing temperatures for theelectrode Ti/Al/Pt/Au in contact with recovered Si-implanted n-type GaN;

[0030]FIG. 7 is a graph showing the dependence of specific contactresistance on annealing time at various annealing temperatures for theelectrode Ti/Al/Au in contact with n-type GaN;

[0031]FIG. 8 is a graph showing the dependence of specific contactresistance on annealing time at various annealing temperatures for theelectrode Ti/Al/Au in contact with unrecovered Si-implanted n-type GaN;

[0032]FIG. 9 is a graph showing the dependence of specific contactresistance on annealing time at various annealing temperatures for theelectrode Ti/Al/Au in contact with recovered Si-implanted n-type GaN;and

[0033]FIG. 10 is a flow chart showing fabrication steps for alight-emitting device of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0034] In the invention, a term “gallium nitride-based III-V groupcompound semiconductor” means a nitride semiconductor of III groupelement including gallium such as GaN, AlGaN, InGaN, or InAlGaN.

[0035] The invention is described in detail below with references beingmade to relevant drawings.

[0036] The invention provides a structure of electrode 8A which includesan ohmic contact layer including such as nitride titanium, titanium,aluminum, chromium, indium, palladium, or an alloy from above-mentionedmetals; a barrier layer over the ohmic contact layer including such asplatinum, tungsten (W), or nickel; and a pad layer over the barrierlayer including such as gold. Since the electrode 8A of the inventionhas a barrier layer, the gold of pad layer is prevented frominterdiffusing and penetrating into the semiconductor device.

[0037] Referring to FIG. 3, which shows an example of the electrode 8Aof the invention. Layers of the structure shown in FIG. 3 are labeledwith same reference numerals designating corresponding layers shown inFIG. 1. As shown in FIG. 3, a GaN buffer layer 2 is formed on asubstrate 1. An n-type semiconductor layer 3 is formed on the bufferlayer 2. The n-type semiconductor layer 3 can be doped with silicon. Anelectrode 8A is formed on the n-type semiconductor layer 3. Theelectrode 8A includes a titanium layer 81, an aluminum layer 82 formedon the titanium layer 81, a platinum layer 83 formed on the aluminumlayer 82, and a gold layer 84 formed on the platinum layer 83. Theelectrode 8A (Ti/Al/Pt/Au) as an example is illustrated below with itssuperior property as an ohmic contact for n-type GaN.

EXAMPLE 1

[0038] A 300 nm GaN buffer layer is grown on a sapphire substrate at520° C. Next, a 2 μm n-type GaN layer is formed on the GaN buffer layerby metal organic chemical vapor deposition (MOCVD) at 1100° C., whereinthe carrier concentration and mobility are 6.7×10¹⁷ cm⁻³ and 367cm²/V-S, respectively.

[0039] Next, the electrode Ti/Al/Pt/Au (25/100/50/200 nm) of theinvention is formed on the n-type GaN layer. Thus formed samples areannealed in nitrogen (N₂) atmosphere at various temperatures (750° C.,850° C., and 950° C.) and various times, and specific contactresistances (ρ_(C)) are measured. Experimental results are shown in FIG.4.

EXAMPLE 2

[0040] A 300 nm GaN buffer layer is grown on a sapphire substrate at520° C. Next, a 2 μm n-type GaN layer is formed on the GaN buffer layerby MOCVD at 1100° C., wherein the carrier concentration and mobility are6.7×10¹⁷ cm⁻³ and 367 cm²/V-S, respectively. Then, Si is implanted intothe n-type GaN layer at an energy of 50 KeV and a dose of 5×10¹⁵ cm⁻².

[0041] Next, the electrode Ti/Al/Pt/Au (25/100/50/200 nm) of theinvention is formed on the Si-implanted n-type GaN layer. Thus formedsamples are annealed under N₂ atmosphere at various temperatures (750°C., 850° C., and 950° C.) and various times, and specific contactresistances (ρ_(C)) are measured. Experimental results are shown in FIG.5.

EXAMPLE 3

[0042] A 300 nm GaN buffer layer is grown on a sapphire substrate at520° C. Next, a 2 μm n-type GaN layer is formed on the GaN buffer layerby MOCVD at 1100° C., wherein the carrier concentration and mobility are6.7×10¹⁷ cm⁻³ and 367 cm² V-S, respectively. Then, Si is implanted intothe n-type GaN layer at an energy of 50 KeV and a dose of 5×10¹⁵ cm⁻².Next, the Si-implanted n-type GaN layer is annealed at 1050° C. under N₂atmosphere for 30 minutes, to aid in the recovery of crystal and toactivate implanted Si of the n-type GaN layer.

[0043] Then, the electrode Ti/Al/Pt/Au (25/100/50/200 nm) of theinvention is formed on the Si-implanted and recovered n-type GaN layer.Thus formed samples are annealed under N₂ atmosphere at varioustemperatures (750° C., 850° C., and 950° C.) and various times, andspecific contact resistances (ρ_(C)) are measured. Experimental resultsare shown in FIG. 6.

Comparative Example 1

[0044] A 300 nm GaN buffer layer is grown on a sapphire substrate at520° C. Next, a 2 μm n-type GaN layer is formed on the GaN buffer layerby MOCVD at 1100° C., wherein the carrier concentration and mobility are6.7×10¹⁷ cm⁻³ and 367 cm²/V-S, respectively.

[0045] Then, a comparative electrode Ti/Al/Au (25/100/200 nm) is formedon the n-type GaN layer. Thus formed samples are annealed under N₂atmosphere at various temperatures (750° C., 850° C., and 950° C.) andvarious times, and specific contact resistances (ρ_(C)) are measured.Experimental results are shown in FIG. 7.

Comparative Example 2

[0046] A 300 nm GaN buffer layer is grown on a sapphire substrate at520° C. Next, a 2 μm n-type GaN layer is formed on the GaN buffer layerby MOCVD at 1100° C., wherein the carrier concentration and mobility are6.7×10¹⁷ cm⁻³ and 367 cm²/V-S, respectively.

[0047] Then, Si is implanted into the n-type GaN layer at an energy of50 KeV and a dose of 5×10¹⁵ cm⁻².

[0048] Next, a comparative electrode Ti/Al/Au (25/100/200 nm) is formedon the Si-implanted n-type GaN layer. Thus formed samples are annealedunder N₂ atmosphere at various temperatures (750° C., 850° C., and 950°C.) and various times, and specific contact resistances (ρ_(C)) aremeasured. Experimental results are shown in FIG. 8.

Comparative Example 3

[0049] A 300 nm GaN buffer layer is grown on a sapphire substrate at520° C. Next, a 2 μm n-type GaN layer is formed on the GaN buffer layerby MOCVD at 1100° C., wherein the carrier concentration and mobility are6.7×10¹⁷ cm⁻³ and 367 cm²/V-S, respectively. Then, Si is implanted intothe n-type GaN layer at an energy of 50 KeV and a dose of 5×10¹⁵ cm⁻².Next, the Si-implanted n-type GaN layer is annealed at 1050° C. under N₂atmosphere for 30 minutes, to aid in the recovery of crystal and toactivate implanted Si of the n-type GaN layer.

[0050] Then, a comparative electrode Ti/Al/Au (25/100/200 nm) is formedon the Si-implanted and recovered n-type GaN layer. Thus formed samplesare annealed under N₂ atmosphere at various temperatures (750° C., 850°C., and 950° C.) and various times, and specific contact resistances(ρ_(C)) are measured. Experimental results are shown in FIG. 9.

[0051] Table 1 below shows details of each of the Examples of theinvention. TABLE 1 Example Example Example Comparative ComparativeComparative 1 2 3 Example 1 Example 2 Example 3 Si-implanted ✓ ✓ ✓ ✓Recovery ✓ ✓ Ti/Al/Au ✓ ✓ ✓ Ti/Al/Pt/Au ✓ ✓ ✓ Results shown in

[0052] Example 1 is for the electrode Ti/Al/Pt/Au of the invention incontact with n-type GaN, and FIG. 4 is a graph showing the dependence ofthe specific contact resistance ρ_(C) for Ti/Al/Pt/Au in contact withGaN on the annealing time at various annealing temperatures. In FIG. 4,the lowest specific contact resistance ρ_(C) is about 8×10⁻⁶ Ω-cm² for750° C., 7×10⁻⁶ Ω-cm² for 850° C., and 7×10⁻⁶ Ω-cm² for 950° C.Comparative Example 1 is for the electrode Ti/Al/Au in contact withn-type GaN, and FIG. 7 is a graph showing he dependence of the specificcontact resistance ρ_(C) for Ti/Al/Au in contact with GaN on annealingtime at various annealing temperatures. When comparing FIG. 4 and FIG. 7we found that the Ti/Al/Pt/Au and Ti/Al/Au multilayer contacts on n-typeGaN exhibit similar values of minimum specific contact resistance.However, the Ti/Al/Pt/Au multilayer has a much better thermal stabilityendurance than that of the Ti/Al/Au multilayer.

[0053] Example 2 is for the electrode Ti/Al/Pt/Au in contact withunrecovered Si-implanted n-type GaN, and FIG. 5 is a graph showing thedependence of the specific contact resistance ρ_(C) for Ti/Al/Pt/Au incontact with Si-implanted GaN on annealing time at various annealingtemperatures. Comparative Example 2 is for the electrode Ti/Al/Au incontact with unrecovered Si-implanted n-type GaN, and FIG. 8 is a graphshowing the dependence of the specific contact resistance ρ_(C) forTi/Al/Au in contact with Si-implanted GaN on annealing time at variousannealing temperatures. As shown in FIGS. 5 and 8, at the annealingtemperature of 750° C., the two kinds of electrode have a similardependence of specific contact resistance on annealing time for 60minutes. It is to be noted that in Comparative Example 2, a minimumspecific contact resistance is obtained at 60 minutes for 750° C., butafter 60 minutes the specific contact resistance greatly increases asthe time increases. However, in Example 2, as shown in FIG. 5, whenannealing at 750° C., the specific contact resistance graduallydecreases as the increase of annealing time.

[0054] In FIG. 5, the minimum specific contact resistance ρ_(C) is7×10⁻⁴ Ω-cm² for 750° C. (beyond 600 minutes), 7×10⁻⁵ Ω-cm² for 850° C.(at 540 minutes), and 2×10⁻⁵ Ω-cm² for 950° C. (at 60 minutes). Inaccordance with the experimental results shown in FIG. 5 and FIG. 8, theelectrode Ti/Al/Pt/Au of the invention has a much better thermalstability than that of the comparative electrode Ti/Al/Au. The thermalstability endurance for the ohmic performance of the Ti/Al/Pt/Aumultilayer annealed at 850° C. and 950° C. is about 540 minutes and 60minutes, respectively, but longer than 600 minutes for annealing at 750°C.

[0055] Example 3 is for the electrode Ti/Al/Pt/Au in contact withSi-implanted and recovered n-type GaN, and FIG. 6 is a graph showing thedependence of the specific contact resistance ρ_(C) for the Ti/Al/Pt/Auin contact with recovered Si-implanted GaN on annealing time at variousannealing temperatures. In FIG. 6, the minimum specific contactresistance ρ_(C) is about 3×10⁻⁶ Ω-cm² for annealing temperatures of750° C., 850° C., and 950° C. Comparative Example 3 is for the electrodeTi/Al/Au in contact with Si-implanted and recovered n-type GaN, and FIG.9 is a graph showing the dependence of specific contact resistance ρ_(C)for the Ti/Al/Au in contact with recovered Si-implanted GaN on annealingtime at various annealing temperatures. When comparing the experimentalresults shown in FIGS. 6 and 9, the comparative electrode Ti/Al/Au andthe electrode Ti/Al/Pt/Au of the invention have similar minimum specificcontact resistance at the same annealing temperature. However, theelectrode Ti/Al/Pt/Au of the invention has a much better thermalstability endurance than that of the Ti/Al/Au multilayer.

[0056] As mentioned above, since the doped magnesium atoms in the p-typeAlGaN layer 6 and the p-type semiconductor layer 7 would form Mg—H bondsand holes are not provided, conventionally a thermal process isperformed after forming the p-type semiconductor layer 7 so as to breakthe Mg—H bonds and activate the p-type AlGaN layer 6 and the p-typesemiconductor layer 7. The thermal process is performed generally at atemperature ranging from 700 to 750° C. for 15 to 60 minutes. However,since the Ti/Al/Pt/Au multilayer of the invention has a high thermalstability endurance, it is beyond question that the activating effect ofthe p-type AlGaN layer 6 and the p-type semiconductor layer 7 can beachieved at the same time when the ohmic contact is formed in theannealing process. Therefore, the fabrication process for thelight-emitting device of the invention can omit the conventionalactivation step, and achieve the same effect in a subsequent fabricationstep. The fabrication process of the light-emitting device in accordancewith the invention is described below with reference being made to FIG.10.

[0057] First, as shown in step 101, a buffer layer 2, an n-typesemiconductor layer 3, an n-type AlGaN layer 4, an active layer 5, ap-type AlGaN layer 6, and a p-type semiconductor layer 7 are formed onthe substrate 1 in this order.

[0058] Next, as shown in step 102, the p-type semiconductor layer 7,p-type AlGaN layer 6, active layer 5, and n-type AlGaN layer 4 arepartially etched away to expose a surface of the n-type semiconductorlayer 3. Here, a part of the n-type semiconductor layer 3 is also etchedaway.

[0059] Next, as shown in step 103, an electrode 8A is formed on then-type semiconductor layer 3. The electrodes 8A can be formed by knowndeposition methods such as evaporation or sputtering. Besides, asdescribed in above-mentioned examples, before forming the electrode 8Aon the n-type semiconductor layer 3, a step of implanting silicon atomsinto the n-type semiconductor layer and a recovery of the n-typesemiconductor layer can be performed.

[0060] Then, as shown in step 104, an annealing process is performed.The object of this step is to lower the ohmic contact resistance of theelectrode 8A. The annealing process is performed at a temperatureranging from 400 to 950° C. Under this annealing condition, activatingeffect of the p-type semiconductor layer 7 can be achieved at the sametime.

[0061] Next, as shown in step 105, the electrode 8B is formed on thep-type semiconductor layer 7 by such as evaporation or sputtering. Afterforming the electrode 8B, an annealing at a low-temperature of below700° C. can be performed to lower the ohmic contact resistance of theelectrode 8B.

[0062] As above, since the annealing and activating effect can beachieved at the same time in step 104, the method for manufacturing acompound semiconductor device provided by the invention is simpler thanconventional fabrication processes, which can lower the costs andincrease the yield.

[0063] While the present invention has been particularly described, inconjunction with specific examples, it is evident that manyalternatives, modifications and variations will be apparent to thoseskilled in the art in light of the foregoing description. It istherefore contemplated that the appended claims will embrace any suchalternatives, modifications and variations as falling within the truescope and spirit of the present invention.

What is claimed is:
 1. A gallium nitride-based III-V group compoundsemiconductor device, comprising: an n-type gallium nitride-based III-Vgroup compound semiconductor layer; and an electrode on said n-typegallium nitride-based III-V group compound semiconductor layer, and saidelectrode having an ohmic contact layer, a barrier layer over said ohmiccontact layer, and a pad layer over said barrier layer.
 2. The device asin claim 1, wherein said barrier layer comprises platinum, tungsten, ornickel.
 3. The device as in claim 1, wherein said electrode is composedof titanium/aluminum/platinum/gold.
 4. A gallium nitride-based III-Vgroup compound semiconductor device, comprising: a substrate having afirst and a second major surfaces; a semiconductor stacked structureformed over the first major surface of said substrate, and saidsemiconductor stacked structure having an n-type gallium nitride-basedIII-V group compound semiconductor layer, an active layer, and a p-typegallium nitride-based III-V group compound semiconductor layer; a firstelectrode on the n-type semiconductor layer, and said first electrodehaving an ohmic contact layer, a barrier layer over said ohmic contactlayer, and a pad layer over said barrier layer; and a second electrodeon the p-type semiconductor layer.
 5. The device as in claim 4, whereinsaid barrier layer comprises platinum, tungsten, or nickel.
 6. Thedevice as in claim 4, wherein said electrode is composed oftitanium/aluminum/platinum/gold.